Polymer crack stop seal ring structure in wafer level package
US9679855B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2016 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Mar 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/11
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, that is configured with trenches that are dry-etched into a surface of the substrate inside an area defined by scribe lines of the substrate. A crack stop structure is provided for the semiconductor device that includes a polymer dielectric layer coating that fills the trenches with a polymer dielectric material and provides a dielectric layer over the surface of the substrate inside the area. The polymer dielectric layer coating and trenches are configured to reduce cracking or chipping of the substrate in the area defined by scribe lines after cutting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.