Semiconductor device and method including an intertial mass element
US9679857B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2016 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Sep 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01P2015/0877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor device comprising a stack of patterned metal layers separated by dielectric layers, the stack comprising a first conductive support structure and a second conductive support structure and a cavity in which an inertial mass element comprising at least one metal portion is conductively coupled to the first support structure and the second support structure by respective conductive connection portions, at least one of said conductive connection portions being designed to break upon the inertial mass element being exposed to an acceleration force exceeding a threshold defined by the dimensions of the conductive connection portions. A method of manufacturing such a semiconductor device is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.