Method of multi-chip wafer level packaging
US9679882B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2016 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Feb 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01029
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of multi-chip wafer level packaging comprises attaching a first semiconductor die to a top side of a wafer, forming a first reconfigured wafer by embedding the first semiconductor die into a first photo-sensitive material layer, forming a first group of through assembly vias in the first photo-sensitive material layer, attaching a second semiconductor die to the first photo-sensitive material layer, forming a second photo-sensitive material layer on top of the first photo-sensitive material layer, wherein the second semiconductor die is embedded in the second photo-sensitive material layer and forming a second group of through assembly vias in the second photo-sensitive material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.