3-D planes memory device
US9679946B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 2015 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Aug 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is a means and a method for manufacturing large three dimensional memory arrays. The present invention is a means and a method for addressing the WL and BL resistance by creating arrays having not only large plane conductors for each of the memory layers (WLs) but also for the opposite polarity common layer (BL). The present invention is also a means and a method to form via interconnections between the substrate logic and the respective layers of a multidimensional array. The present invention is also a way to operate an array in which the select device is unipolar but the array is above to be operated in a bipolar way. This facilitates a bipolar operation for memory cell technologies such as Resistive RAM (e.g., RRAM, ReRAM and Memresistors).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.