Translation lookaside buffer for guest physical addresses in a virtual machine
US9684605B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2015 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Feb 23, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/68
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of an invention for a guest-physical address translation lookaside buffer are disclosed. In an embodiment, a processor includes an instruction decoder, a control register, and memory address translation hardware. The instruction decoder is to receive an instruction to transfer control of the processor to guest software to execute on a virtual machine. The virtual machine is to have a plurality of resources to be controlled by a virtual machine monitor. The virtual machine monitor is to execute on a host machine having a host-physical memory to be accessed using a plurality of host-physical addresses. The plurality of resources is to include a guest-physical memory. The guest software is to access the guest-physical memory using a plurality of guest-virtual addresses. The control register is to store a pointer to a plurality of virtual address page tables. The memory address translation hardware is to translate, without causing a virtual machine exit, guest-virtual addresses to host-physical addresses using the plurality of virtual address page tables and a plurality of extended page tables. The memory address translation hardware includes a virtual address translation l…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.