Overlapping precharge and data write
US9685210B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2016 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Jul 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a plurality of memory cells and a plurality of bitlines. Each of the plurality of bitlines is coupled to a corresponding one of the plurality of memory cells. A precharge circuit precharges each of the plurality of bitlines before a read operation and precharges all but one of the plurality of bitlines following the read operation. A write driver drives the one of the plurality of bitlines following the read operation. A method includes precharging each of a plurality of bitlines before a read operation. Each of the plurality of bitlines is coupled to a corresponding one of a plurality of memory cells. The method further includes precharging all but one of the plurality of bitlines following the read operation and driving the one of the plurality of bitlines following the read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.