Memory with bit line control
US9685224B2 · kind B2 · utility
1Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 2015 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | May 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory comprises a first set of memory cells coupled between a first data line and a second data line. The memory also includes a first input/output (I/O) circuit coupled to the first data line and the second data line. The first I/O circuit is also coupled to a first control line to receive a first control signal and coupled to a first select line to receive a first select signal. The first I/O circuit is configured to selectively decouple the first data line and the second data line from the first I/O circuit during a sleep mode based on the first control signal and the first select signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.