Selective and non-selective barrier layer wet removal
US9685406B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2016 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Apr 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device includes forming a dielectric layer on a substrate, forming a plurality of openings in the dielectric layer, conformally depositing a barrier layer on the dielectric layer and on sides and a bottom of each one of the plurality of openings, depositing a contact layer on the barrier layer in each one of the plurality of openings, removing a portion of each contact layer from each one of the plurality of openings, and removing a portion of the barrier layer from each one of the plurality of openings, wherein at least the removal of the portion of the barrier layer is performed using an etchant including: (a) a compound selected from group consisting of -azole, -triazole, and combinations thereof; (b) a compound containing one or more peroxy groups; (c) one or more alkaline metal hydroxides; and (d) water.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.