Semiconductor package device
US9685422B2 · kind B2 · utility
2Cited by
3References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2015 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Dec 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package may include a first chip located over a substrate. The semiconductor package may include a second chip located over the substrate and adjacent to the first chip. The semiconductor package may include a test micro-bump located at a layer below the first chip and above the substrate, and electrically coupled to an external connection member through a first path. The semiconductor package may include a normal micro-bump located at a layer below the first chip and above the substrate, and electrically coupled to the second chip through a second path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.