Isolated III-N semiconductor devices
US9685545B2 · kind B2 · utility
9Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2015 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Nov 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device with a substrate, a low defect layer formed in a fixed position relative to the substrate, and a barrier layer comprising III-N semiconductor material formed on the low-defect layer and forming an electron gas in the low-defect layer. The device also has a source contact, a drain contact, and a gate contact for receiving a potential, the potential for adjusting a conductive path in the electron gas and between the source contact and the drain contact. Lastly, the device has a one-sided PN junction between the barrier layer and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.