Patterning methods, methods of fabricating semiconductor devices using the same, and semiconductor devices fabricated thereby
US9685606B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2015 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Dec 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A patterning method includes forming an etch-target layer on a substrate, forming mask patterns on the etch-target layer, and etching the etch-target layer using the mask patterns as an etch mask to form patterns spaced apart from each other. The etching process of the etch-target layer includes irradiating the etch-target layer with an ion beam, whose incident energy ranges from 600 eV to 10 keV. A recess region is formed in the etch-target layer between the mask patterns, and the ion beam is incident onto a bottom surface of the recess region at a first angle with respect to a top surface of the substrate and is incident onto an inner side surface of the recess region at a second angle with respect to the inner side surface of the recess region. The first angle ranges from 50° to 90° and the second angle ranges from 0° to 40°.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.