Parallel slice processor with dynamic instruction stream mapping

US9690585B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Lee Evan Eisen · Round Rock, US
• Hung Q. Le · Austin, US
• Jentje Leenstra · Nagold, DE
• Jose E. Moreira · Dobbs Ferry, US
• Bruce Joseph Ronchetti · Austin, US
• Brian W. Thompto · Austin, US
• Albert J. Van Norstrand, Jr. · Round Rock, US

Key dates

• Filing date: Jun 10, 2014
• Grant date: Jun 27, 2017
• Expiry date: Jan 3, 2035

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/5083
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method of operation of a processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues coupled by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the relationship between the slices and instruction streams according to execution requirements for the instruction streams and the availability of resources in the instruction execution slices. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution and ordinary instruction execution on a per-instruction basis. Instructions having an operand width greater than the width of a single instruction execution slice may be processed by multiple instruction execution slices configured to act in concert for the particular instructions. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.