Processing of multiple instruction streams in a parallel slice processor

US9690586B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Lee Evan Eisen · Round Rock, US
• Hung Q. Le · Austin, US
• Jentje Leenstra · Nagold, DE
• Jose E. Moreira · Dobbs Ferry, US
• Bruce Joseph Ronchetti · Austin, US
• Brian W. Thompto · Austin, US
• Albert J. Van Norstrand, Jr. · Round Rock, US

Key dates

• Filing date: Jun 12, 2014
• Grant date: Jun 27, 2017
• Expiry date: Nov 5, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F15/8007
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method of managing instruction execution for multiple instruction streams using a processor core having multiple parallel instruction execution slices provides instruction processing flexibility. An event is detected indicating that either resource requirement or resource availability for a subsequent instruction of an instruction stream will not be met by the instruction execution slice currently executing the instruction stream. In response to detecting the event, dispatch of at least a portion of the subsequent instruction is made to another instruction execution slice. The event may be a compiler-inserted directive, may be an event detected by logic in the processor core, or may be determined by a thread sequencer. The execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution, ordinary instruction execution, wide instruction execution. When an execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.