System and method for fusing instructions queued during a time window defined by a delay counter
US9690591B2 · kind B2 · utility
2Cited by
22References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2008 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Jun 11, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique to enable efficient instruction fusion within a computer system is disclosed. In one embodiment, processor logic delays the processing of a first instruction for a threshold amount of time if the first instruction within an instruction queue is fusible with a second instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.