High performance persistent memory for region-centric consistent and atomic updates
US9690716B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2015 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Apr 6, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/251
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a non-persistent cache, wherein the transaction is to create a mapping from a virtual address space to a memory region identified by a memory region identifier (MRID) in the persistent memory, and tag a cache line of the non-persistent cache with the MRID, in which the cache line is associated with a cache line status, and a cache controller, in response to detecting a failure event, to selectively evict contents of the cache line to the memory region identified by the MRID based on the cache line status.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.