Prioritized path tracing in statistical timing analysis of integrated circuits
US9690899B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2015 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Aug 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of the present disclosure can include methods for prioritized path tracing in a statistical timing analysis of integrated circuits. Methods of the present disclosure can include: determining a required arrival time for a merge point in a statistical timing graph, the merge point having a plurality of associated input edges; calculating a plurality of edge slack distributions for each of the plurality of input edges and the required arrival time at the merge point; projecting a representative edge slack from each of the plurality of edge slack distributions; identifying a most critical input edge based on the plurality of representative edge slacks; generating a prioritized listing of input edges from lowest-value representative edge slack to highest-value representative edge slack; and tracing a next-most critical input edge of the prioritized listing, subsequent to tracing a path from the most critical edge to a source point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.