Transistor gain cell with feedback
US9691445B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2015 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Apr 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The gain cell also includes a write transistor, retention element and read transistor. Each of the transistors includes a respective first diffusion connection, gate connection and second diffusion connection. The write transistor first diffusion connection is connected to the write bit line input and the write transistor gate connection is connected to the write trigger input. The read transistor first diffusion connection being connected to the read bit line output and the second diffusion connection is connected to the read trigger input. The retention element buffers between write transistor and the read transistor during data retention. The retention element also connects or disconnects a write transistor diffusion connection to/from a constant voltage in accordance with a retained data level at the read transistor gate connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.