Via and chamfer control for advanced interconnects
US9691659B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2016 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Sep 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32131
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a semiconductor structure includes etching a via opening through an interlevel dielectric to a metal conductor. A contiguous metal liner is deposited onto exposed surfaces of the substrate. The substrate is exposed to a gaseous ion plasma to remove portions of the metal liner that are horizontally oriented and to reduce a height of the metal liner from portions thereof that are vertically oriented. Subsequently, a trench opening is formed in the interlevel dielectric, wherein the trench opening is connected with the via opening, wherein at least a portion of the metal liner remains on sidewall surfaces within the via opening during the forming of the trench opening. A diffusion barrier liner is deposited within the trench opening and the via opening. A conductive material is formed within remaining portions of the trench opening and the via opening to define the interconnect structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.