Three-dimensional structured memory devices
US9691785B2 · kind B2 · utility
8Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2015 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Nov 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/324
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.