Systems and methods involving fast-acquisition lock features associated with phase locked loop circuitry
US9692429B1 · kind B1 · utility
28Cited by
48References
23Claims
0Family size
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Inventor
Key dates
| Filing date | Nov 6, 2015 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Nov 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0807
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed relating to fields of clock/data acquisition or handling, such as clock/data locking and the like. In one exemplary implementation, phase lock loop (PLL) circuitry may comprise voltage controlled oscillator (VCO) circuitry, phase frequency detector, converting circuitry, and frequency detector (FD) circuitry that outputs a frequency difference signal proportional to frequency difference between frequencies of a feedback clock signal and a reference clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.