Memory transaction having implicit ordering effects
US9696928B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2014 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Nov 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1663
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In at least some embodiments, a processor core executes a code segment including a memory transaction and a non-transactional memory access instructions preceding the memory transaction in program order. The memory transaction includes at least an initiating instruction, a transactional memory access instruction, and a terminating instruction. The initiating instruction has an implicit barrier that imparts the effect of ordering execution of the transactional memory access instruction within the memory transaction with respect to the non-transactional memory access instructions preceding the memory transaction in program order. Executing the code segment includes executing the transactional memory access instruction within the memory transaction concurrently with at least one of the non-transactional memory access instructions preceding the memory transaction in program order and enforcing the barrier implicit in the initiating instruction following execution of the initiating instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.