High performance interconnect physical layer
US9697158B2 · kind B2 · utility
0Cited by
7References
19Claims
0Family size
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Key dates
| Filing date | Nov 12, 2014 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | May 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reset of a synchronization counter is synchronized to an external deterministic signal. Entry into the link transmitting state is further synchronized with the deterministic signal. A target latency is identified for a serial data link. A data sequence is received synchronized with a synchronization counter associated with the data link. Target latency can be maintained using the data sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.