Partial SOI on power device for breakdown voltage improvement
US9698024B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2014 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Jul 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.