Low-stress dual underfill packaging
US9698072B2 · kind B2 · utility
7Cited by
15References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2015 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Dec 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates generally to flip chip technology and more particularly, to a method and structure for reducing internal packaging stresses, improving adhesion properties, and reducing thermal resistance in flip chip packages by using more than one underfill material deposited in different regions of the flip chip interface. According to one embodiment, a method of forming a first underfill in an interior region of an interface such that a periphery region of the interface remains open, and forming a second underfill in the periphery region is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.