Interface layer for gate stack using O3 post treatment
US9698234B2 · kind B2 · utility
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8References
26Claims
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Key dates
| Filing date | Mar 24, 2015 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Mar 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Exemplary embodiments provide for fabricating a field effect transistor (FET) with an interface layer for a gate stack using an O3 post treatment. Aspects of the exemplary embodiments include: forming a semiconductor body upon a substrate; cleaning the surface of the semiconductor body; depositing a first dielectric layer on the semiconductor body; performing an O3 treatment to form a new interface layer that incorporates material from the substrate and material from the first dielectric layer; and performing gate stack processing, including deposition of a gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.