Method for the surface etching of a three-dimensional structure
US9698250B2 · kind B2 · utility
1Cited by
1References
18Claims
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Key dates
| Filing date | Sep 16, 2015 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Sep 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for etching a dielectric layer located on the surface of a three-dimensional structure formed on a face of a substrate oriented along a plane of a substrate, which includes a step of implanting ions so as to directionally create a top layer in the dielectric layer. Such top layer is thus not formed everywhere. Then, the layer in question is removed, except on the predefined zones, such as flanks of a transistor gate. A selective etching of the dielectric layer is executed relative to the material of the residual part of the top layer and relative to the material of the face of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.