Symmetric LDMOS transistor including a well of a first type of conductivity and wells of an opposite second type of conductivity

US9698257B2 · kind B2 · utility

Assignee

• AMS AG · AT

Inventors

• Jong Mun Park · Graz, AT
• Georg Röhrer · Graz, AT

Key dates

• Filing date: May 30, 2011
• Grant date: Jul 4, 2017
• Expiry date: Jul 21, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/126

Abstract

The symmetric LDMOS transistor comprises a semiconductor substrate (1), a well (2) of a first type of conductivity in the substrate, and wells (3) of an opposite second type of conductivity. The wells (3) of the second type of conductivity are arranged at a distance from one another. Source/drain regions (4) are arranged in the wells of the second type of conductivity. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) on the gate dielectric. A doped region (10) of the second type of conductivity is arranged between the wells of the second type of conductivity at a distance from the wells. The gate electrode has a gap (9) above the doped region (10), and the gate electrode overlaps regions that are located between the wells (3) of the second type of conductivity and the doped region (10).