Transistor and semiconductor memory device
US9698272B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2016 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Sep 16, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a transistor includes a first electrode, a second electrode, a current path between the first and second electrodes, the current path including an oxide semiconductor layer, a control terminal which controls an on/off action of the current path, an insulating layer between the control terminal and the oxide semiconductor layer, a first oxide layer between the first electrode and the oxide semiconductor layer, the first oxide layer being different from the oxide semiconductor layer, and a second oxide layer between the second electrode and the oxide semiconductor layer, the second oxide layer being different from the oxide semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.