Dynamic sense amplifier with offset compensation
US9698765B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 22, 2016 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Feb 22, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a first and second inverters each having a signal input, signal output, high voltage supply terminal, and low voltage supply terminal. The signal input of the first inverter is coupled to the signal output of the second inverter, and the signal input of the second inverter is coupled to the signal output of the first inverter. A first transistor has a first conduction terminal coupled to a power supply node, a second conduction terminal coupled to the high voltage supply terminal of the first inverter, and a control terminal coupled to a first node. A second transistor has a first conduction terminal coupled to the power supply node, a second conduction terminal coupled to the high voltage supply terminal of the second inverter, and a control terminal coupled to a second node. First and second bit lines are capacitively coupled to the first and second nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.