Low-power phase interpolator with wide-band operation
US9698970B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 3, 2016 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Mar 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An example clock delivery system includes a phase-locked loop (PLL) configured to generate a plurality of input clocks, a phase interpolator configured to receive the plurality of input clocks and generate a plurality of output clocks, and a clock data recovery (CDR) circuit configured to receive the plurality of output clocks. The phase interpolator includes a decoder having a plurality of inputs configured to receive binary codes and a respective plurality of outputs configured to output thermometer codes, and a mixer circuitry segmented into a plurality of unit circuits that are enabled or disabled based on bits of the thermometer codes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.