Patent · US Active

Digital modulation jitter compensation for polar transmitter

US9699014B2 · kind B2 · utility

0Cited by

4References

12Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Markus Schimper · Erding, DE
Franz Kuttner · Braunau am Inn, AT

Key dates

Filing date	Mar 5, 2012
Grant date	Jul 4, 2017
Priority date	—
Expiry date	Apr 28, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH04L27/367
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

This disclosure is directed towards techniques and methods of suppressing the effect of modulated clock jitter in a digital to analog conversion (DAC) circuit of a polar modulator in a transceiver. A phase locked loop (PLL) in a modulator circuit may introduce a deterministic jitter in DAC generated pulses which may lead to amplitude variations in the DAC generated pulses. The clock jitter may change the duty cycle of the input amplitude to the DAC which may result in a variation of the output of the DAC generated pulse. A digital pre-distortion or digital multiplier circuit may be introduced before the DAC circuit to increase or decrease the DAC amplitude to compensate for the pulse width modulation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.