Peripheral clock management
US9703313B2 · kind B2 · utility
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2References
11Claims
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Assignee
Inventor
Key dates
| Filing date | Sep 15, 2015 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Sep 15, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock generator for use in an electronic system comprising an integrated circuit such as a microcontroller. A plurality of oscillators are selectively enabled to produce a respective plurality of oscillator signals. For each of a plurality of clock outputs, a mux selects a respective one of the oscillator signals in response to a respective select signal provided by a clocked facility. The selected oscillator signal is gated out as the respective clock signal in response to a respective gate signal also provided by the clocked facility.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.