Sharing TLB mappings between contexts
US9703566B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2011 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Mar 9, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some implementations, a processor may include a data structure, such as a translation lookaside buffer, that includes an entry containing first mapping information having a virtual address and a first context associated with a first thread. Control logic may receive a request for second mapping information having the virtual address and a second context associated with a second thread. The control logic may determine whether the second mapping information associated with the second context is equivalent to the first mapping information in the entry of the data structure. If the second mapping information is equivalent to the first mapping information, the control logic may associate the second thread with the first mapping information contained in the entry of the data structure to share the entry between the first thread and the second thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.