Method and apparatus for detecting or correcting multi-bit errors in computer memory systems
US9703625B1 · kind B1 · utility
1Cited by
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10Claims
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Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Mar 31, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for detecting a data bit inversion (DBI) error in a memory system is disclosed. The method and system comprise calculating an error correcting code (ECC) from each of the 8 beats of a burst of data such that no more than one bit per byte is included in each ECC calculation. The method and system further include determining if there is an inversion of one byte in the burst.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.