Circuits, apparatuses, and methods for correcting data errors
US9703633B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2015 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Sep 8, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One example apparatus includes a first circuit configured to receive first and second data words, to correct one or more errors in the first data word, to merge the corrected first data word and the second data word responsive to a control signal to generate a final merged data word, and to provide the final merged data word to a write circuit. The apparatus also includes a second circuit configured to also receive the first and second data words, to preliminarily merge the first and second data words responsive to the control signal to generate an initial merged data word, to generate an initial parity code for the initial merged data word, to correct the initial parity code, and to provide the corrected parity code to the write circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.