Guided memory buffer allocation
US9703696B1 · kind B1 · utility
1Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2013 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Mar 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for explicit organization of memory allocation on an integrated circuit (IC) are provided. In particular, a programmable logic designer may incorporate specific mapping requests into programmable logic designs. The mapping requests may specify particular mappings between one or more data blocks (e.g., memory buffers) of a host program to one or more physical memory banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.