Intra-run design decision process for circuit synthesis
US9703920B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2015 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Jul 1, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of performing an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design are described. The method includes executing a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters, and determining a quality measure associated with each of the two or more scenarios. The method also includes performing the intra-run decision by eliminating one or more of the two or more scenarios for execution in a subsequent stage of the synthesis based on the quality measure associated with each of the two or more scenarios.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.