Patent · US Active

Stressing and testing semiconductor memory cells

US9704567B1 · kind B1 · utility

1Cited by

10References

17Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Michael Kugel · Eppelheim, DE
Stefan Payer · Stuttgart, DE
Wolfgang Penth · Holzgerlingen, DE
Juergen Pille · Stuttgart, DE

Key dates

Filing date	Jul 12, 2016
Grant date	Jul 11, 2017
Priority date	—
Expiry date	Jul 12, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/1204
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory cell that is readable through a bit line and addressable through a word line can be stressed using a method that includes addressing the memory cell, through the word line, for an addressing time. The memory cell can be stressed by applying a stress voltage to the bit line for a stress voltage time that overlaps with the addressing time for a stress time Δt. A method for testing a memory cell can include writing a data value into the memory cell, stressing the memory cell, reading a stored value from the memory cell and determining whether the stored value corresponds to the data value. A testable memory array can include at least one memory cell that is addressable through a word line and readable through a bit line and a stress circuit for applying a stress voltage to the bit line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.