High voltage architecture for non-volatile memory
US9704585B2 · kind B2 · utility
2Cited by
8References
9Claims
0Family size
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Key dates
| Filing date | Sep 18, 2015 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Sep 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F30/2823
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.