Semiconductor memory device and operating method thereof
US9704587B1 · kind B1 · utility
8Cited by
0References
19Claims
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Assignee
Inventor
Key dates
| Filing date | Jun 6, 2016 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Jun 6, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided herein are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include: drain select transistor coupled to a bit line; a source select transistor coupled to a source line; a plurality of memory cells coupled in series between the drain select transistor and the source select transistor; and a peripheral circuit configured to successively apply a discharge control voltage to memory cells in sequence from a memory cell adjacent to the source select transistor to a memory cell adjacent to the drain select transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.