Interposers of 3-dimensional integrated circuit package systems and methods of designing the same

US9704766B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Sandeep Kumar Goel · Dublin, US
• Mill-Jer Wang · Hsinchu, TW
• Chung-Sheng Yuan · Baoshan, TW
• Tom C. Chen · Hsinchu, TW
• Chao-Yang Yeh · New Taipei, TW
• Chin-Chou Liu · Taipei, TW
• Yun-Han Lee · Hengshan, TW

Key dates

• Filing date: May 27, 2011
• Grant date: Jul 11, 2017
• Expiry date: Dec 6, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/157
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer.