Fan-out and heterogeneous packaging of electronic components
US9704809B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2013 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Dec 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/157
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure pertain to a packaging structure configured for providing heterogeneous packaging of electronic components and a process for making same. The packaging structure includes a carrier substrate having a plurality of cavities formed therein. The packaging structure further includes a first die and a second die. The first die is at least substantially contained within a first cavity included in the plurality of cavities. The second die is at least substantially contained within a second cavity included in the plurality of cavities. The first die is fabricated via a first fabrication technology, and the second die is fabricated via a second fabrication technology, the second fabrication technology being different than the first fabrication technology. The packaging structure also includes electrical interconnect circuitry connected to (e.g., for electrically connecting) the first die, the second die and/or the carrier substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.