Package substrate and semiconductor package including the same
US9704815B2 · kind B2 · utility
1Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 2016 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | May 16, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package substrate may include an insulating substrate, internal circuits and a warpage-suppressing member. The insulating substrate may have a plurality of mount regions in which semiconductor chips may be mounted, and a peripheral region. The internal circuits may be arranged in the mount regions. The warpage-suppressing member is different from the semiconductor chips and may be arranged in at least one of the mount regions to suppress a warpage of the insulating substrate. Thus, warpage of the package substrate may be suppressed during a reflow process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.