Hybrid bond pad structure
US9704827B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2015 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Jun 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06544
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a multi-dimensional integrated chip having a redistribution layer vertically extending between integrated chip die, which is laterally offset from a back-side bond pad. The multi-dimensional integrated chip has a first integrated chip die with a first plurality of metal interconnect layers disposed within a first inter-level dielectric layer arranged onto a front-side of a first semiconductor substrate. The multi-dimensional integrated chip also has a second integrated chip die with a second plurality of metal interconnect layers disposed within a second inter-level dielectric layer abutting the first ILD layer. A bond pad is disposed within a recess extending through the second semiconductor substrate. A redistribution layer vertically extends between the first plurality of metal interconnect layers and the second plurality of metal interconnect layers at a position that is laterally offset from the bond pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.