Three dimensional integrated circuit
US9704835B2 · kind B2 · utility
28Cited by
42References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2016 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Jan 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method comprises providing a first substrate having dielectric structures and conductive structures. Ions are implanted into the first substrate, the ions traveling through the dielectric structures and the conductive structures to define a cleave plane in the first substrate. The first substrate is cleaved at the cleave plane to obtain a cleaved layer having the dielectric structure and the conductive structures. The cleaved layer is used to form a three-dimensional integrated circuit device having a plurality of stacked integrated circuit (IC) layers, the cleaved layer being one of the stacked IC layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.