VDMOS having shielding gate electrodes in trenches and method of making the same

US9704986B2 · kind B2 · utility

Assignee

• International Onizuka Electronics Limited · CN

Inventors

• Mau Lam Lai · Singapore, SG
• Yeuk Yin Mong · Sha Tin, CN
• Duc Chau · San Jose, US

Key dates

• Filing date: Jun 13, 2016
• Grant date: Jul 11, 2017
• Expiry date: Jun 13, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/256

Abstract

A VDMOS includes a substrate; an epitaxial layer; first and second trenches defined in the epitaxial layer; a shielding gate and a control gate formed in the trenches; a body region formed at the epitaxial layer and between the first and second trenches; a N+ source region formed at the body region; a distinct doping region formed in the epitaxial layer underneath the body region, extending towards bottoms of the trenches; a channel defined between the N+ source region and epitaxial layer adjacent to the trenches; an insulating layer defining a contact hole extending into the body region and the first trench; a P+ body pickup region formed in the body region corresponding to the contact hole; and a metal layer haying a butting contact filled in the contact hole, connecting the N+ source region, P+ body pickup region, and control gate and/or shielding gate in the first trench.