Shared cache data movement in thread migration
US9710303B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 6, 2013 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | May 19, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies are generally described for methods, systems, and processors effective to migrate a thread. The thread may be migrated from the first core to the second core. The first and the second core may be configured in communication with a first cache. The first core may generate a request for a first data block from the first cache. In response to a cache miss in the first cache for the first data block, the first core may generate a request for the first data block from a memory. The first core may coordinate with a second cache to store the first data block in the second cache. The thread may be migrated from the second core to a third core. The second core and third core may be configured in communication with the second cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.