Processors, methods, systems, and instructions to support live migration of protected containers

US9710401B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Carlos V. Rozas · Portland, US
• Mona Vij · Hillsboro, US
• Rebekah M. Leslie-Hurd · Portland, US
• Krystof C. Zmudzinski · Forest Grove, US
• Somnath Chakrabarti · Portland, US
• Francis X. McKeen · Portland, US
• Vincent R. Scarlata · Beaverton, US
• Simon P. Johnson · Beaverton, US
• Ilya Alexandrovich · Haifa, IL
• Gilbert Neiger · Hillsboro, US
• Vedvyas Shanbhogue · Austin, US
• Ittai Anati · Ramat HaSharon, IL

Key dates

• Filing date: Jun 26, 2015
• Grant date: Jul 18, 2017
• Expiry date: Jun 26, 2035

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/1052
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processor includes a decode unit to decode an instruction that is to indicate a page of a protected container memory, and a storage location outside of the protected container memory. An execution unit, in response to the instruction, is to ensure that there are no writable references to the page of the protected container memory while it has a write protected state. The execution unit is to encrypt a copy of the page of the protected container memory. The execution unit is to store the encrypted copy of the page to the storage location outside of the protected container memory, after it has been ensured that there are no writable references. The execution unit is to leave the page of the protected container memory in the write protected state, which is also valid and readable, after the encrypted copy has been stored to the storage location.