Method and apparatus for performing register retiming in the presence of timing analysis exceptions
US9710591B1 · kind B1 · utility
3Cited by
28References
24Claims
0Family size
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Key dates
| Filing date | Feb 20, 2015 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Oct 21, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.