Methods, systems, and articles of manufacture for enhancing timing analyses with reduced timing libraries for electronic designs
US9710593B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2015 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Oct 14, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are techniques for enhancing timing analyses with reduced timing libraries for electronic designs. These techniques determine dominance relations for multiple timing models for timing analyses and generate a dominance adjacency data structure based at least in part upon the dominance relations. The dominance adjacency data structure may be stored at a first location of a non-transitory computer accessible storage medium. The plurality of timing models may be reduced into a reduced set of timing models at least by providing the dominance adjacency data structure as an input to a transformation and further by transforming the dominance adjacency data structure with the transformation into the reduced set of timing models that are used in timing analyses for an electronic design or a portion thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.